Ring oscillators are analog circuits created out of an odd number of inverting stages used to measure various physical parameters. The oscillators are designed such that the frequency period of oscillation correlates well with the physical parameter being measured. Historically, these circuits were only attached to chip IO but recently they have been embedded in chip circuitry to make them system-accessible for various purposes. In the past in order to test measure ring oscillators, special off chip analog test equipment capable of performing as an oscilloscope and spectrum analyzer was used to measure the speed of the oscillator. The use of the prior art of the off chip analog test equipment to measure oscillator speeds is a tedious, inaccurate and inefficient method of interactively testing each of a number of embedded ring oscillators individually and requires excessive test time and complex test software support algorithms. Further, the analog testing sequences and test results are incompatible with the chip I/O circuits. Adding analog support functions to each of the oscillator circuits to enable their testing would be one approach, but this would also result in excessive chip real estate and energy consumption.
Currently, VLSI devices incorporate structure to perform digital on-chip test functions. These built-in test and diagnostic functions are based on several Design for Test (DFT) techniques using scan chains testing techniques, such as Level Sensitive Scan Design (LSSD) using associated Logic & Array Built-in-self-test (LBIST & ABIST) devices, on-product-clock-generation (OPCG) techniques, and similar devices and techniques. Many of the BIST designs are further based on Signature Analysis (SA) concepts as response data compression methods. As described by E. B. Eichelberger and T. W. Williams in an article entitled “A Logic Design Structure for LSI Testability” on pages 462-468 of the Proceedings of the 14th Design Automation conf., LSSD rules impose a clocked structure on logic circuit memory elements such as latches and registers and require these memory elements be tied together to form a shift register scan path so that they are accessible for use as test input and output points. Therefore, digital test input signals can be introduced or digital test results observed wherever one of the memory elements occurs in the logic circuit. Being able to enter the logic circuit at any memory element for introducing test signals or observing test results, allows the combinational and sequential logic to be treated as much simpler combinational logic for testing purposes thus considerably simplifying test generation and analysis. Patents describing LSSD and built-in self test techniques include U.S. Pat. No. 3,783,254; No. 3,784,907; No. 3,961,252 No. 4,513,418, No. 6,181,614, No. 5,805,789, No. 5,659,551 and No. 5,659,551. The subject matter of these patents are hereby included by reference.